Conventional amorphous silicon (a-Si) image arrays typically comprise an array of pixels and an associated matrix of rows and columns of address lines to electrically access each pixel. Each pixel has a photodiode and thin film transistor (TFT). The gate of each TFT is coupled to a scan line and the source (or alternatively the drain) of each TFT is coupled to a data line. These address lines are used to read the signal from respective pixel photodiodes.
Image lag affects a-Si image sensors when a pixel is exposed to sufficient illumination to populate deep traps in the a-Si, which traps release charge long after the pixel has been exposed. The effect is greatly excerbated when a photodiode is exposed to sufficient intensity such that the voltage across the photodiode drops to zero and the built-in field collapses. Under these conditions, charged carriers diffuse throughout the bulk material in the diode and distort the built-in field characteristics. When the diode is returned to the dark, it takes many seconds for the carriers distributed among the deep traps to emit and low leakage currents to be restored. This results in a ghost image that remains for several tens of seconds after the image was taken.
One prior art solution to reduce image lag is to reduce the density of bulk traps in the diode material. The trap density in a-Si, however, can only be reduced to a certain level through materials engineering. This limit is on the order of about 3-5×1015 cm−3.
Another prior art solution is to increase the built-in field. This can be done by using a high built-in potential layer such as microcrystalline P+ doped a-Si or by reducing the thickness of the photodiode. Microcrystalline P+ doped a-Si, however, only adds about 0.5 V to the built-in potential. Using a large built-in potential improves image lag, but under high enough exposure conditions the voltage across the diode will always drop to zero and increase image lag. Thus, the benefit of reduced image lag provided by increasing the effective field across the diode must be weighed against the inevitable increase in sensor dark current and, in the case of thinner photodiodes, increased diode capacitance and increased pixel noise.
To achieve higher resolution, full fill factor a-Si image arrays extend the sensor into a continuous layer on top of the array. In contrast to a conventional image array in which each pixel is defined by a stand alone photodiode, a full fill factor a-Si image array improves the pixel fill factor by using continuous layers of a-Si and P+ doped a-Si. As shown in FIG. 1, the pixels in a full fill factor array 10 are defined only by collection electrodes comprising patterned metal contacts 20 and N+ doped a-Si 30. The full fill factor sensor array, further includes continuous layers of intrinsic a-Si 40, P+ doped a-Si 50, and indium-tin-oxide 60 (ITO). The device comprises a plurality of pixels coupled to a plurality of gate lines and data lines (not shown). Gate lines and data lines are typically disposed in the array substantially perpendicular to each other in a matrix arrangement such that data lines overlie gate lines at each pixel in a crossover region. Each pixel also includes a TFT 70. The gate lines are coupled to the gate electrodes of TFT 70 and the signals on these lines are used to cause TFT 70 to become conductive or non-conductive. The data lines are coupled to the drains of TFT 70.
Full fill factor image arrays also suffer from image lag. In addition to image lag, however, full fill factor image arrays also suffer blooming. Blooming occurs when a pixel is strongly illuminated and the charge moves laterally in the continuous a-Si layer. As the pixel saturates, the surface charges up to the bias voltage Vbias screening the vertical field. The only direction for the charge to move is laterally towards higher, less exposed regions. This lateral movement of charge results in adjacent pixels being activated by the laterally spread charge. These adjacent pixels are read-out as having been exposed when, in fact, only the strongly illuminated pixel was exposed.
Conventional TFT full fill factor sensor arrays also lack a means for testing the TFT matrix prior to depositing the overlying collection electrode and sensor layer. One solution is to add storage capacitors at each pixel and charge them through the data lines or by an electron-beam. The charge at each TFT in the array could then be measured. This solution, however, requires a capacitor at each pixel making it harder to form smaller pixels. Another disadvantage is that the added capacitors add increased pixel noise to the electronic noise of the array.
In light of the foregoing, there is a need for a method and device to reduce the image lag and blooming in a-Si sensor arrays. There is also a need for a method and device for testing the TFT matrix and effecting repairs without damaging the overlying collection electrodes and sensor layer.